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2.3. Architecture and Organization (AR)

Computing professionals spend considerable time writing efficient code to solve a particular problem in an application domain. As the shift from sequential to parallel processing occurs, a deeper understanding of the underlying computer architectures is necessary. Architecture can no longer be viewed as a black box where principles from one architecture can be applied to another. Instead, programmers should look inside the black box and use specific components to enhance system performance and energy efficiency.

The Architecture and Organization (AR) knowledge area aims to develop a deeper understanding of the hardware environments upon which almost all computing is based, and the relevant interfaces provided to higher software layers. The target hardware comprises low-end embedded system processors up to high-end enterprise multiprocessors.

The topics in this knowledge area will benefit students by enabling them to appreciate the fundamental architectural principles of modern computer systems, including the challenge of harnessing parallelism to sustain performance and energy improvements into the future. This KA will help computer science students depart from the black box approach and become more aware of the underlying computer system and the efficiencies specific architectures can achieve.

Knowledge Area (KA)	CS Core	KA Core
2.3.1 Digital Logic and Digital Systems		3
2.3.2 Machine-Level Data Representation	1
2.3.3 Assembly Level Machine Organization	1	2
2.3.4 Memory Hierarchy	6
2.3.5 Interfacing and Communication	1
2.3.6 Functional Organization		2
2.3.7 Performance and Energy Efficiency		3
2.3.8 Heterogeneous Architectures		2
2.3.9 Secure Processor Architectures		2
2.3.10 Quantum Architectures		2
2.3.11 Sustainability Issues	Elective

2.3.1. AR/Digital Logic and Digital Systems  (KA Core: 3 hrs) ↑ Back to top

Topics:
Core

• Combinational vs sequential logic/field programmable gate arrays (FPGAs):
• Fundamental combinational
• Sequential logic building block enumerate
• Computer-aided design tools that process hardware and architectural representations
• High-level synthesis:
• Register transfer notation
• Hardware description language (e.g., Verilog/VHDL/Chisel) enumerate
• System-on-chip (SoC) design flow
• Physical constraints:
• Gate delays
• Fan-in and fan-out
• Energy/power
• Speed of light enumerate

Learning Outcomes:
Core:

1. Discuss the progression of computer technology components from vacuum tubes to VLSI, from mainframe computer architectures to the organization of warehouse-scale computers [Debate]
2. Describe parallelism and data dependencies between and within components in a modern heterogeneous computer architecture [Describe]
3. Explain the relationship between parallelism and power consumption [Explain]
4. Construct the design of basic building blocks for a computer: arithmetic-logic unit (gate-level), registers (gate-level), central processing unit (register transfer-level), and memory (register transfer-level) [Create]
5. Evaluate simple building blocks (e.g., arithmetic-logic unit, registers, movement between registers) of a simple computer design [Evaluate]
6. Analyze the timing behavior of a pipelined processor, identifying data dependency issues [Analyze]

2.3.2. AR/Machine-Level Data Representation  (CS Core: 1 hr) ↑ Back to top

Topics:
Core

• Overview and history of computer architecture
• Bits, bytes, and words
• Unsigned, signed and two's complement representations
• Numeric data representation and number bases:
• Fixed-point
• Floating-point enumerate
• Representation of non-numeric data
• Representation of records, arrays and UTF data types

Learning Outcomes:
Core:

1. Discuss why everything in computers are data, including instructions [Debate]
2. Explain how fixed-length number representations can affect accuracy and precision [Explain]
3. Describe how negative integers are stored in sign-magnitude and two's-complement representations [Describe]
4. Discuss how different formats can represent numerical data [Debate]
5. Explain the bit-level representation of non-numeric data, such as characters, strings, records, and arrays [Explain]
6. Translate numerical data from one format to another [Translate]
7. Describe how a single adder (without overflow detection) can handle both signed (two's complement) and unsigned (binary) input without "knowing" which format a given input is using [Describe]

2.3.3. AR/Assembly Level Machine Organization  (CS Core: 1 hr, KA Core: 2 hrs) ↑ Back to top

Topics:
Core

• von Neumann machine architecture
• Control unit: instruction fetch, decode, and execution
• Introduction to SIMD vs MIMD and the Flynn taxonomy
• Shared memory multiprocessors/multicore organization
• Instruction set architecture (ISA) (e.g., x86, ARM and RISC-V):
• Fixed vs variable-width instruction sets
• Instruction formats
• Data manipulation, control, I/O
• Addressing modes
• Machine language programming
• Assembly language programming enumerate
• Subroutine call and return mechanisms
• I/O and interrupts
• Heap, static, stack, and code segments

Learning Outcomes:
Core:

1. Discuss how the classical von Neumann functional units are implemented in embedded systems, particularly on-chip and off-chip memory [Debate]
2. Describe how instructions are executed in a classical von Neumann machine, with extensions for threads, multiprocessor synchronization, and SIMD execution [Describe]
3. Assess an example diagram with instruction-level parallelism and hazards to describe how they are managed in typical processor pipelines [Assess]
4. Discuss how instructions are represented at the machine level and in the context of a symbolic assembler [Debate]
5. Map an example of high-level language patterns into assembly/machine language notations [Map]
6. Contrast different instruction formats considering aspects such as addresses per instruction and variable-length vs fixed-length formats [Contrast]
7. Analyze a subroutine diagram to comment on how subroutine calls are handled at the assembly level [Analyze]
8. Describe basic concepts of interrupts and I/O operations [Describe]
9. Write a simple assembly language program for string/array processing and manipulation [Write]

2.3.4. AR/Memory Hierarchy  (CS Core: 6 hrs) ↑ Back to top

Topics:
Core

• Memory hierarchy: the importance of temporal and spatial locality
• Main memory organization and operations
• Persistent memory (e.g., SSD, standard disks)
• Latency, cycle time, bandwidth, and interleaving
• Cache memories:
• Address mapping
• Block size
• Replacement and store policy
• Prefetching enumerate
• Multiprocessor cache coherence
• Virtual memory (hardware support)
• Fault handling and reliability
• Reliability:
• Error coding
• Data compression
• Data integrity enumerate
• Processing In-Memory (PIM)

Learning Outcomes:
Core:

1. Using a memory system diagram, identify the main types of memory technology (e.g., SRAM, DRAM) and their relative cost and performance [Analyze]
2. Measure the effect of memory latency on running time [Evaluate]
3. Enumerate the functions of a system with virtual memory management [Enumerate]
4. Compute average memory access time under various cache and memory configurations and mixes of instruction and data references [Compute]

2.3.5. AR/Interfacing and Communication  (CS Core: 1 hr) ↑ Back to top

Topics:
Core

• I/O fundamentals:
• Handshaking and buffering
• Programmed I/O
• Interrupt-driven I/O enumerate
• Interrupt structures: vectored and prioritized, interrupt acknowledgment
• I/O devices (e.g., mouse, keyboard, display, camera, sensors, actuators)
• External storage, physical organization, and drives
• Buses fundamentals:
• Bus protocols
• Arbitration
• Direct-memory access (DMA) enumerate

Learning Outcomes:
Core:

1. Analyze an interrupt control diagram to comment on how interrupts are used to implement I/O control and data transfers [Analyze]
2. Enumerate various types of buses in a computer system [Enumerate]
3. List the advantages of magnetic disks and contrast them with those of solid-state disks [List]

2.3.6. AR/Functional Organization  (KA Core: 2 hrs) ↑ Back to top

Topics:
Core

• Implementation of simple datapaths, including instruction pipelining, hazard detection, and resolution (e.g., stalls, forwarding)
• Control unit:
• Hardwired implementation
• Microprogrammed realization enumerate
• Instruction pipelining
• Introduction to instruction-level parallelism (ILP)

Learning Outcomes:
Core:

1. Compare alternative implementation of datapaths in modern computer architectures [Compare]
2. Produce a set of control signals for adding two integers using hardwired and microprogrammed implementations [Produce]
3. Discuss instruction-level parallelism using pipelining and significant hazards that may occur [Debate]
4. Design a complete processor, including datapath and control [Design]
5. Compute the average cycles per instruction for a given processor and memory system implementation [Compute]

2.3.7. AR/Performance and Energy Efficiency  (KA Core: 3 hrs) ↑ Back to top

Topics:
Core

• Performance-energy evaluation (introduction): performance, power consumption, memory, and communication costs
• Branch prediction, speculative execution, out-of-order execution, Tomasulo's algorithm
• Enhancements for vector processors and GPUs
• Hardware support for multithreading:
• Race conditions
• Lock implementations
• Point-to-point synchronization
• Barrier implementation enumerate
• Scalability
• Alternative architectures including VLIW/EPIC, accelerators, and other special purpose processors
• Dynamic voltage and frequency scaling (DVFS)
• Dark Silicon

Learning Outcomes:
Core:

1. Discuss performance and energy efficiency evaluation metrics [Debate]
2. Analyze a speculative execution diagram and write about the decisions that can be made [Analyze]
3. Create a GPU performance-watt benchmarking diagram [Create]
4. Write a multithreaded program that adds (in parallel) elements of two integer vectors [Write]
5. Recommend a set of design choices for alternative computer architectures [Recommend]
6. Enumerate key concepts associated with dynamic voltage and frequency scaling [Enumerate]
7. Measure energy savings improvement for an 8-bit integer quantization compared to a 32-bit quantization [Evaluate]

2.3.8. AR/Heterogeneous Architectures  (KA Core: 2 hrs) ↑ Back to top

Topics:
Core

• SIMD and MIMD architectures (e.g., General-Purpose GPUs, TPUs, and NPUs)
• Heterogeneous memory systems:
• Shared memory versus distributed memory
• Volatile vs non-volatile memory
• Coherence protocols enumerate
• Domain-Specific Architectures (DSAs):
• Machine Learning Accelerator
• In-networking computing
• Embedded systems for emerging applications
• Neuromorphic computing
• Edge computing devices enumerate
• Packaging and integration solutions such as 3DIC and chiplets
• Machine learning in architecture design:
• AI algorithms for workload analysis
• Optimization of architecture configurations for performance and power efficiency enumerate

Learning Outcomes:
Core:

1. Analyze a system diagram with alternative parallel architectures, e.g., SIMD and MIMD, and identify the key differences [Analyze]
2. Discuss what memory-management issues are found in multiprocessors that are not present in uniprocessors and how these issues might be resolved [Debate]
3. Indicate the differences between memory backplane, processor memory interconnect, and remote memory via networks, their implications for access latency, and their impact on program performance [Differentiate]
4. Discuss how you would determine when to use a domain-specific accelerator instead of a general-purpose CPU [Debate]
5. Enumerate key differences in architectural design principles between a vector and scalar-based processing unit [Enumerate]
6. List the advantages and disadvantages of a PIM architecture [List]

2.3.9. AR/Secure Processor Architectures  (KA Core: 2 hrs) ↑ Back to top

Topics:
Core

• Principles of Secure Hardware:
• Security Risk Analysis, Asset Protection, and Threat Model
• Cryptographic Acceleration with Hardware
• Support for virtualization (e.g., OS isolation) enumerate
• Roots of trust in hardware, Physically Unclonable Functions (PUF)
• Hardware Random Number Generators
• Memory protection extensions:
• Runtime pointer bounds checking (e.g., buffer overflow)
• Protection at the microarchitectural level
• Protection at the ISA level enumerate
• Trusted Execution Environment (TEE):
• Trusted Computer Base Protections
• Protecting virtual machines
• Protecting containers
• Trusted software modules (Enclaves) enumerate
• Homomorphic encryption for privacy-preserving data processing

Learning Outcomes:
Core:

1. Discuss principles of secure hardware, exploring a framework for risk analysis and asset protection [Debate]
2. Summarize how Physically Unclonable Functions (PUF) can be a unique device identifier in security applications [Summarize]
3. Distinguish a random number generator with dedicated hardware support from generators without hardware dedicated to generating entropy [Distinguish]
4. List the advantages and disadvantages of memory protection at the ISA level [List]
5. Describe key design issues of a trusted execution environment (TEE) to support virtual machines [Describe]

2.3.10. AR/Quantum Architectures  (KA Core: 2 hrs) ↑ Back to top

Topics:
Core

• Principles:
• The wave-particle duality principle
• The uncertainty principle in the double-slit experiment
• What is a Qubit? Superposition, interference, and measurement. Photons as qubits
• Systems of two qubits, Entanglement, Bell states, The No-Signaling theorem enumerate
• Axioms of QM: superposition principle, measurement axiom, unitary evolution
• Single qubit gates for the circuit model of quantum computation: X, Z, H
• Two qubit gates and tensor products, working with matrices
• The No-Cloning Theorem. The Quantum Teleportation protocol
• Algorithms:
• Simple quantum algorithms: Bernstein-Vazirani, Simon's algorithm
• Implementing Deutsch-Josza with Mach-Zehnder Interferometers
• Quantum factoring (Shor's Algorithm)
• Quantum search (Grover's Algorithm) enumerate
• Implementation aspects:
• The physical implementation of qubits
• Classical control of a Quantum Processing Unit (QPU)
• Error mitigation and control, NISQ and beyond
• Measurement approaches enumerate
• Emerging Applications:
• Post-quantum encryption
• The Quantum Internet
• Adiabatic quantum computation (AQC) and quantum annealing enumerate

Learning Outcomes:
Core:

1. Discuss how a quantum object produced as a particle propagates like a wave and is detected as a particle with a probability distribution corresponding to the wave [Debate]
2. Discuss the quantum-level nature that is inherently probabilistic [Debate]
3. Express your view on entanglement that can be used to create non-classical correlations, but there is no way to use quantum entanglement to send messages faster than the speed of light [Evaluate]
4. Describe quantum parallelism and the role of constructive vs destructive interference in quantum algorithms given the probabilistic nature of measurement(s) [Describe]
5. Analyze a code snippet providing the role of quantum Fourier transform (QFT) in Shor's algorithm [Analyze]
6. Write a program to implement Shor's algorithm in a simulator, highlighting the classical components and aspects of Shor's algorithm [Write]
7. Enumerate the specifics of each qubit modality (e.g., trapped ion, superconducting, silicon spin, photonic, quantum dot, neutral atom, topological, color center, electron-on-helium) [Enumerate]
8. Contrast AQC with the gate model of quantum computation and the problems each is better suited to solve [Contrast]

2.3.11. AR/Sustainability Issues ↑ Back to top

Topics:
Non Core

• Environmental impacts of implementation decisions:
• Sustainability goals, resource consumption, and economic viability
• Carbon footprint, hardware electronic waste
• The energy footprint of data centers at various workloads (e.g., AI model training and use)
• Guidelines for sustainable design standards enumerate

Learning Outcomes:
NonCore:

1. Assess the environmental impacts of a given project's deployment (e.g., the energy consumption of CPUs and GPUs, contribution to e-waste, and effect of hardware virtualization in data centers) [Assess]