5.21. Computer Systems Architecture (Mandatory)

5.21. Computer Systems Architecture (Mandatory)

Figure 5.21: Connection Map. CS221 Computer Systems Architecture

5.21.1. Justification ↑ Back to top

A deep understanding of computer architecture is essential for developing high-performance software and understanding the hardware-software interface. This course explores how computers execute instructions, manage memory, and communicate with external devices. By studying the internal organization of processors and the hierarchy of memory systems, students gain the ability to optimize code for specific hardware architectures and understand the trade-offs in modern system design.

5.21.2. Generales Goals ↑ Back to top

  1. Understand the principles of digital logic and data representation.
  2. Understand the organization of the Central Processing Unit (CPU).
  3. Master the basics of assembly language and instruction set architecture.
  4. Analyze the memory hierarchy, including cache memory and virtual memory.
  5. Evaluate performance improvements through pipelining and parallelism.

5.21.3. Contribution to Outcomes ↑ Back to top

AG-C09) Design and Development of Solutions: Designs, implements, and evaluates solutions for complex computing problems. (Usage)
AG-C03) Individual and Team Work: Performs effectively as an individual and as a member or leader in diverse teams. (Usage)

5.21.4. Content ↑ Back to top

5.21.4.1. Assembly Level Machine Organization (20 hours) [Skills AG-C03,AG-C09] ↑ Back to top

Bibliography: (Patterson and Hennessy, 2020; Harris and Harris, 2012)

Topics

  1. von Neumann machine architecture
  2. Control unit: instruction fetch, decode, and execution
  3. Introduction to SIMD vs MIMD and the Flynn taxonomy
  4. Shared memory multiprocessors/multicore organization
  5. Instruction set architecture (ISA) (e.g., x86, ARM and RISC-V):
    1. Fixed vs variable-width instruction sets
    2. Instruction formats
    3. Data manipulation, control, I/O
    4. Addressing modes
    5. Machine language programming
    6. Assembly language programming enumerate
    7. Subroutine call and return mechanisms
    8. I/O and interrupts
    9. Heap, static, stack, and code segments

    Learning Outcomes

    1. Discuss how the classical von Neumann functional units are implemented in embedded systems, particularly on-chip and off-chip memory [Debate]
    2. Describe how instructions are executed in a classical von Neumann machine, with extensions for threads, multiprocessor synchronization, and SIMD execution [Describe]
    3. Assess an example diagram with instruction-level parallelism and hazards to describe how they are managed in typical processor pipelines [Assess]
    4. Discuss how instructions are represented at the machine level and in the context of a symbolic assembler [Debate]
    5. Map an example of high-level language patterns into assembly/machine language notations [Map]
    6. Contrast different instruction formats considering aspects such as addresses per instruction and variable-length vs fixed-length formats [Contrast]
    7. Analyze a subroutine diagram to comment on how subroutine calls are handled at the assembly level [Analyze]
    8. Describe basic concepts of interrupts and I/O operations [Describe]
    9. Write a simple assembly language program for string/array processing and manipulation [Write]
    5.21.4.2. Memory Hierarchy (18 hours) [Skills AG-C03,AG-C09] ↑ Back to top

    Bibliography: (Patterson and Hennessy, 2020; Stallings, 2015)

    Topics

    1. Memory hierarchy: the importance of temporal and spatial locality
    2. Main memory organization and operations
    3. Persistent memory (e.g., SSD, standard disks)
    4. Latency, cycle time, bandwidth, and interleaving
    5. Cache memories:
      1. Address mapping
      2. Block size
      3. Replacement and store policy
      4. Prefetching enumerate
      5. Multiprocessor cache coherence
      6. Virtual memory (hardware support)
      7. Fault handling and reliability
      8. Reliability:
        1. Error coding
        2. Data compression
        3. Data integrity enumerate
        4. Processing In-Memory (PIM)

        Learning Outcomes

        1. Using a memory system diagram, identify the main types of memory technology (e.g., SRAM, DRAM) and their relative cost and performance [Analyze]
        2. Measure the effect of memory latency on running time [Evaluate]
        3. Enumerate the functions of a system with virtual memory management [Enumerate]
        4. Compute average memory access time under various cache and memory configurations and mixes of instruction and data references [Compute]
        5.21.4.3. Interfacing and Communication (8 hours) [Skills AG-C03,AG-C09] ↑ Back to top

        Bibliography: (Patterson and Hennessy, 2020; Tanenbaum and Austin, 2012)

        Topics

        1. I/O fundamentals:
          1. Handshaking and buffering
          2. Programmed I/O
          3. Interrupt-driven I/O enumerate
          4. Interrupt structures: vectored and prioritized, interrupt acknowledgment
          5. I/O devices (e.g., mouse, keyboard, display, camera, sensors, actuators)
          6. External storage, physical organization, and drives
          7. Buses fundamentals:
            1. Bus protocols
            2. Arbitration
            3. Direct-memory access (DMA) enumerate

            Learning Outcomes

            1. Analyze an interrupt control diagram to comment on how interrupts are used to implement I/O control and data transfers [Analyze]
            2. Enumerate various types of buses in a computer system [Enumerate]
            3. List the advantages of magnetic disks and contrast them with those of solid-state disks [List]
            5.21.4.4. Functional Organization (8 hours) [Skills AG-C03,AG-C09] ↑ Back to top

            Bibliography: (Harris and Harris, 2012; Patterson and Hennessy, 2020)

            Topics

            1. Implementation of simple datapaths, including instruction pipelining, hazard detection, and resolution (e.g., stalls, forwarding)
            2. Control unit:
              1. Hardwired implementation
              2. Microprogrammed realization enumerate
              3. Instruction pipelining
              4. Introduction to instruction-level parallelism (ILP)

              Learning Outcomes

              1. Compare alternative implementation of datapaths in modern computer architectures [Compare]
              2. Produce a set of control signals for adding two integers using hardwired and microprogrammed implementations [Produce]
              3. Discuss instruction-level parallelism using pipelining and significant hazards that may occur [Debate]
              4. Design a complete processor, including datapath and control [Design]
              5. Compute the average cycles per instruction for a given processor and memory system implementation [Compute]
              5.21.4.5. Heterogeneous Architectures (10 hours) [Skills AG-C03,AG-C09] ↑ Back to top

              Bibliography: (Patterson and Hennessy, 2020; Stallings, 2015)

              Topics

              1. SIMD and MIMD architectures (e.g., General-Purpose GPUs, TPUs, and NPUs)
              2. Heterogeneous memory systems:
                1. Shared memory versus distributed memory
                2. Volatile vs non-volatile memory
                3. Coherence protocols enumerate
                4. Domain-Specific Architectures (DSAs):
                  1. Machine Learning Accelerator
                  2. In-networking computing
                  3. Embedded systems for emerging applications
                  4. Neuromorphic computing
                  5. Edge computing devices enumerate
                  6. Packaging and integration solutions such as 3DIC and chiplets
                  7. Machine learning in architecture design:
                    1. AI algorithms for workload analysis
                    2. Optimization of architecture configurations for performance and power efficiency enumerate
                    3. Data-Oriented Design (DOD): organizing data in memory (array-of-structures vs. structure-of-arrays) to maximize cache locality and exploit SIMD vectorization; contrast and complementarity with the object-oriented paradigm.

                    Learning Outcomes

                    1. Analyze a system diagram with alternative parallel architectures, e.g., SIMD and MIMD, and identify the key differences [Assessment]
                    2. Discuss what memory-management issues are found in multiprocessors that are not present in uniprocessors and how these issues might be resolved [Assessment]
                    3. Indicate the differences between memory backplane, processor memory interconnect, and remote memory via networks, their implications for access latency, and their impact on program performance [Familiarity]
                    4. Discuss how you would determine when to use a domain-specific accelerator instead of a general-purpose CPU [Assessment]
                    5. Enumerate key differences in architectural design principles between a vector and scalar-based processing unit [Familiarity]
                    6. List the advantages and disadvantages of a PIM architecture [Familiarity]
                    7. Restructure a collection of objects (AoS) into a DOD layout (SoA) and measure the performance impact [Usage].
                    5.21.4.6. Secure Processor Architectures (8 hours) [Skills AG-C03,AG-C09] ↑ Back to top

                    Bibliography: (Patterson and Hennessy, 2020; Anderson, 2020)

                    Topics

                    1. Principles of Secure Hardware:
                      1. Security Risk Analysis, Asset Protection, and Threat Model
                      2. Cryptographic Acceleration with Hardware
                      3. Support for virtualization (e.g., OS isolation) enumerate
                      4. Roots of trust in hardware, Physically Unclonable Functions (PUF)
                      5. Hardware Random Number Generators
                      6. Memory protection extensions:
                        1. Runtime pointer bounds checking (e.g., buffer overflow)
                        2. Protection at the microarchitectural level
                        3. Protection at the ISA level enumerate
                        4. Trusted Execution Environment (TEE):
                          1. Trusted Computer Base Protections
                          2. Protecting virtual machines
                          3. Protecting containers
                          4. Trusted software modules (Enclaves) enumerate
                          5. Homomorphic encryption for privacy-preserving data processing

                          Learning Outcomes

                          1. Discuss principles of secure hardware, exploring a framework for risk analysis and asset protection [Debate]
                          2. Summarize how Physically Unclonable Functions (PUF) can be a unique device identifier in security applications [Summarize]
                          3. Distinguish a random number generator with dedicated hardware support from generators without hardware dedicated to generating entropy [Distinguish]
                          4. List the advantages and disadvantages of memory protection at the ISA level [List]
                          5. Describe key design issues of a trusted execution environment (TEE) to support virtual machines [Describe]

                          5.21.5. Bibliography ↑ Back to top

                          Patterson, D. A. and Hennessy, J. L. (2020). Computer Organization and Design RISC-V Edition: The Hardware Software Interface. Morgan Kaufmann, 2nd edition.

                          Harris, D. and Harris, S. (2012). Digital Design and Computer Architecture. Morgan Kaufmann, 2nd edition.

                          Stallings, W. (2015). Computer Organization and Architecture: Designing for Performance. Pearson, 10th edition.

                          Tanenbaum, A. S. and Austin, T. (2012). Structured Computer Organization. Pearson, 6th edition.

                          Anderson, R. J. (2020). Security Engineering: A Guide to Building Dependable Distributed Systems. Wiley, 3rd edition.

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